The ASIC Network
A network of university clubs teaching students to design real computer chips, together. Open documentation, shared progress, and a growing list of clubs across the world.
What it is
The ASIC Network is a collective of university ASIC and VLSI clubs: independent student groups, working in the open, sharing what we learn.
Chip design is hard to break into and easy to do alone. The network pools that effort. Right now that means shared documentation and a biweekly cadence where clubs trade progress, flows, and gotchas. No gatekeeping, no silos. Just one signal across independent clubs building together.
Documentation
Open, shared docs. Tooling notes, design flows, and guides any member club can use and contribute to.
Biweekly updates
Every two weeks clubs share progress and blockers. A simple rhythm to keep things moving and learn from each other.
Open on GitHub
Everything lives in the open. Fork the repos, file issues, send pull requests.
Community
A shared Discord where clubs talk day to day. Register below to get an invite.
Connected universities
Every university is pinned to its real location on the globe. Filled nodes are joined; hollow ones are in progress. Lines connect joined universities to show the network.
Click any node to see details. The map reads straight from universities.csv: add a row with lat/lng, push, and a new pin appears.
Tutorials
Two tracks, both written by the network and free for anyone to use. Start at the first page and work forward: no prior tool experience assumed.
Everything lives on GitHub alongside the rest of our docs, so if something is wrong or missing, open an issue or send a pull request.
Analog
Schematic capture, device sizing, simulation, and layout. The path from a single transistor to a working analog block.
Open analog tutorials → 02Digital
RTL, synthesis, place and route, and signoff. The path from Verilog you have written to a layout you can hand off.
Open digital tutorials →Support student chip design
The ASIC Network connects active student hardware clubs across North America, Europe, and Asia. Every new chapter we onboard naturally extends the reach of our existing partners. We keep the partner list small and deliberate: the trust of our member clubs is our most important asset, so we are highly selective about who we work with.
We work with three kinds of partners, each supporting a different relationship with the student hardware community.
Recruiting Pipeline
Students in the ASIC Network do real chip design, not coursework. When you post roles through the network, chapter leads surface candidates they know personally and would vouch for. You get a curated shortlist instead of a resume drop. Students get interviews with companies that actually understand hardware hiring.
Ecosystem Reach
The biggest gap between school and industry is professional tool fluency. Tooling partners support workshops and standardized flows so students train on real EDA environments. They graduate ready to contribute in your stack from day one.
Tape-Out Support
Most student designs never leave a simulator. Silicon partners make the best projects real by funding tape-outs. Every chip is openly documented: PDK used, what worked, what did not. Transparent, student-generated evidence of your platform's real-world performance.
We are actively expanding with some of the strongest student hardware communities globally. Partnering early means your reach grows into every new chapter we onboard, automatically and with no contracts to revisit. If your company is serious about working with the next generation of hardware talent, we would like to talk.
Get in touchRegister your club
Got an ASIC or VLSI club at your university? Fill out the form and we'll get you plugged into the network.